Flash memory devices may be used in whatever application where it is desirable to store information that should be held even when the flash memory devices are not powered. In general, each flash memory device comprises a matrix of memory cells. Each memory cell typically comprises a floating gate metal oxide semiconductor (MOS) transistor having a drain terminal, a source terminal, and a gate terminal, in a completely similar manner to a standard MOS transistor, with the addition of a further floating gate region that is buried within an oxide layer so as to be electrically insulated.
An information bit is physically stored within each memory cell in the form of electric charge within the floating gate, which defines a corresponding threshold voltage of the transistor. In particular, the memory cell is programmed at a high threshold voltage (electric charges being trapped within the floating gate) and erased at a low threshold voltage (floating gate being free from electric charges). The flash memory device may be programmed at the level of individually selected memory cells, whereas it may be erased only at the level of groups of selected memory cells (for example, one or more pages of memory cells each one being formed in a corresponding insulated well).
As it is known, the erasing of the selected pages takes place by applying a set of erasing pulses with increasing value to each one of them, until all the respective memory cells have been erased. However, this may generate (in such selected pages) depleted memory cells, whose transistors have threshold voltages lower than the low threshold voltage (so that they may be in conduction even if not selected). For this reason, the erasing typically comprises, downstream of the application of the set of erasing pulses, a recovery phase wherein any depleted memory cells are identified and subjected to a soft-programming operation for recovering them to the (erased) non-depleted condition.
If however such recovery phase is not carried out (or completed), such as following up undesired interruptions of electrical power with consequent incorrect shutdown of the flash memory device, the presence of depleted memory cells may cause malfunctions (for example, reading errors). To reduce these occurrences, in the state of the art there are approaches that provide for storing information relating to the erasing of the selected pages within a register of service memory cells. For such purpose, an address of the selected pages is written upon starting of their erasing, and a corresponding flag is written upon completion of the erasing thereof (by programming corresponding memory cells of the service register). In this way, at each power-on of the flash memory device, any selected page that is not completely erased (address being written and flag being not written) may be identified and subjected to erasing (with corresponding soft-programming). However, once the service register has been filled (after a certain number of erasing), it may be necessary to completely erase it before being able to use it again. Therefore, it may be desirable that the service register be relatively large (for limiting its erasing), with consequent significant area occupation. In any case, at each (unavoidable) erasing of the service register, the flash memory device has long latency times, and thus a reduced efficiency.
In addition, the presence of parasitic couplings involves a not complete insulation between the memory cells so that the selection of one or more memory cells (or pages) may cause electrical noise on memory cells (or pages) being not selected, and hence an alteration of the information bits stored therein. Therefore, the memory cells are periodically subjected to a refresh of their content, for example, by a specific re-programming algorithm. However, the refresh, being usually carried out on entire sectors of the memory device (each one typically comprising a large number of pages), requires long execution times, which further reduces the efficiency of the flash memory device.